1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which enables selective production of different semiconductor memory devices operating at different external power-supply voltages.
2. Description of the Background Art
General-purpose DRAMs (Dynamic Random Access Memory), that have been wide spread as semiconductor memory devices, include SDR (Single Data Rate)-SDRAMs (synchronous-DRAMs), each of which transmits data, an address signal and a control signal to/from an external source in synchronization with a rise of an external clock, and DDR (Double Data Rate)-SDRAMs, each of which transmits data, an address signal and a control signal to/from an external source in synchronization with both the rise and a fall of the external clock. The DDR-SDRAMs have been made to attain improved performance by making a transfer rate thereof twice as fast as that of the SDR-SDRAMs.
An SDR-SDRAM is different from a DDR-SDRAM not only in the transfer rate of data or the like, but also in a power-supply voltage and an interface. Currently, the power-supply voltage and a power-supply voltage for output of the SDR-SDRAM are 3.3V and the interface is LVTTL (Low Voltage-TTL) for 3.3V. On the other hand, the power-supply voltage and the power-supply voltage for output of the DDR-SDRAM is 2.5V, and the interface is SSTL-2 (Stub Series Terminated Logic) for 2.5V.
With development of high-density DRAMs, a semiconductor process has come to involve more miniaturization process, and thus a break-down voltage of a gate oxide film of an MOS transistor has been reduced. This requires reduction of an operating voltage in order to attain higher reliability of the DRAMs. However, a personal computer as a main application product of the DRAMs utilizes, in a system with one standard, a plurality of generations of DRAMs, making it difficult to reduce the operation voltage of DRAM. Thus, in order to address the problem described above, a voltage down converter is provided within a chip in a DRAM, for an example, to reduce an external power-supply voltage of 3.3V to an internal power-supply voltage of 2.5V. As a result, the SDR-SDRAM is supplied with the external power-supply voltage of 3.3V, and is operated at the internal power-supply voltage of 2.5V which is down-converted from the external power-supply voltage of 3.3V by the voltage down converter. The DDR-SDRAM is supplied with the external power-supply; voltage of 2.5V to be operated.
It is then necessary to produce different products with different power-supply voltages for the SDR-SDRAMs and for the DDR SDRAMs when DRAMs are produced, while both of the SDR-SDRAM and the DDR-SDRAM are around in the market.
Though an SDR-SDRAM and a DDR-SDRAM are different in their interfaces, many parts in memory cores are common. Thus, a semiconductor memory device can be designed, in consideration of its productivity, such that an SDR-SDRAM and a DDR-SDRAM can be selectively produced, for example, by simply replacing a metal mask. An internal circuit of the SDRAM is divided into three parts as follows: (1) a part usable for both SDR and DDR, (2) a part used only for SDR, and (3) a part used only for DDR. When the SDR-SDRAM is to be produced, (2) the part used only for SDR is activated and (3) the part used only for DDR is inactivated. When, on the other hand, the DDR-SDRAM is to-be produced, (2) the part used only for SDR is inactivated and (3) the part used only for DDR is activated.
Thus, as shown in FIG. 19, a semiconductor memory device 500 enabling selective production of the SDR-SDRAM and the DDR-SDRAM includes a switch 120, a common circuit 130, exclusive circuits 140 and 150, an external power-supply line 160, an internal power-supply line 170, a power-supply line 180 and a voltage down converter 190.
When the DDR-SDRAM operated at the external power-supply voltage of 2.5V is to be produced, switch 120 is connected to external power-supply line 160 by a metal mask, and when the SDR-SDRAM operated at the internal power-supply voltage of 2.5V which has been down-converted from the external power-supply voltage of 3.3V is to be produced, it is connected to internal power-supply line 170 by the metal mask. Common circuit 130 is connected to power-supply line 180 and is operated at the external power-supply voltage of 2.5V and the internal power-supply voltage of 2.5V which has been down-converted from the external power-supply voltage of 3.3V. Exclusive circuit 140 is connected to internal power-supply line 170 and is operated at the internal power-supply voltage of 2.5V only when the external power-supply voltage of 3.3V is supplied thereto. Exclusive circuit 150 is connected to external power-supply line 160 and is operated only at the external power-supply voltage-of 2.5V.
External power-supply line 160 supplies the external power-supply voltage of 2.5V or 3.3V to switch 120, exclusive circuit 150 and voltage down converter 190. Internal power-supply line 170 is connected to voltage down converter 190 to supply the internal power-supply voltage of 2.5V which has been down-converted by voltage down converter 190 to switch 120 and exclusive circuit 140.
Voltage down converter 190 down-converts the external power-supply voltage of 3.3V, supplied from external power-supply line 160, to the internal power-supply voltage of 2.5V.
When external power-supply line 160 is supplied with the external power-supply voltage of 3.3V, i.e., when the SDR-SDRAM is produced, voltage down converter 190 down-converts the external power-supply voltage of 3.3V to the internal power-supply voltage of 2.5V, and supplies the down-converted voltage to internal power-supply line 170. Switch 120 is connected to internal power-supply line 170 by the metal mask. Then, common circuit 130 and exclusive circuit 140 are supplied with the internal power-supply voltage, and common circuit 130 inputs/outputs various signals to/from exclusive circuit 140, for writing and reading data. Exclusive circuit 150 operated only at the external power-supply voltage of 2.5V is then inactivated by an inactivation signal from common circuit 130, and is supplied with the external power-supply voltage of 3.3V by external power-supply line 160.
On the other hand, when external power-supply line 160 is supplied with the external power-supply voltage of 2.5V, i.e., when the DDR-SDRAM is produced, internal power-supply line 170 to which exclusive circuit 140 is connected is further connected to external power-supply line 160 by a switch (not shown), and exclusive circuit 140 is supplied with the external power-supply voltage of 2.5V. Further, switch 120 is connected to external power-supply line 160. Then, common circuit 130 and exclusive circuit 150 are supplied with the external power-supply voltage of 2.5V. Common circuit 130 inputs/outputs various signals to/from exclusive circuit 150 for reading and writing data. Exclusive circuit 140 operated only at the external power-supply voltage of 3.3V is inactivated by an inactivation signal from common circuit 130.
However, if a signal of a level H (logical high) is output from common circuit 130 to exclusive circuit 150 in order to inactivate exclusive circuit 150 when SDR-SDRAM is to be produced, current disadvantageously flows through from external power-supply line 160 to a ground terminal (such current is hereinafter referred to as xe2x80x9cthrough currentxe2x80x9d) in exclusive circuit 150, making it impossible to produce a semiconductor memory device with low power consumption.
Referring to FIG. 20, common circuit 130 includes an inverter 135 provided between a power-supply node 133 and a ground terminal 134. Inverter 135 includes a P-channel MOS transistor 131 and an N-channel MOS transistor 132. In inverter 135, a signal of a level L (logical low) is input from a node N20 and a signal of level H is output to a node N21. Power-supply node 133 is supplied with the internal power-supply voltage of 2.5V.
Exclusive circuit 150 includes inverters 156 and 159, each provided between a power-supply node 153 and a ground terminal 154. Inverter 156 includes a P-channel MOS transistor 151 and an N-channel MOS transistor 152. Inverter 159 includes a P-channel MOS transistor 157 and an N-channel MOS transistor 158. Power-supply node 153 is supplied with the external power-supply voltage of 3.3V.
In inverter 135 of common circuit 130, power-supply node 133 is supplied with the internal power-supply voltage of 2.5V, so that the signal of level H to be output to node N21 has a voltage of 2.5V. Thus, a voltage of 2.5V is input to inverter 156 in exclusive circuit 150. A voltage of 2.5V is then applied to the gate terminals of P-channel MOS transistor 151 and N-channel MOS transistor 152. P-channel MOS transistor 151 will not be completely turned off, but rather weakly turned on, since the external power-supply voltage of 3.3V is applied to the source terminal of the transistor. Further, N-channel MOS transistor 152 is turned on. As a result, through current 155 flows from power-supply node 153 to ground terminal 154 in inverter 156, and inverter 156 outputs a medium voltage between 0V and 3.3V to a node N22.
The medium voltage between 0V and 3.3V is input to inverter 159, so that P-channel MOS transistor 157 is weakly turned on and N-channel MOS transistor 158 is turned on. As a result, through current 161 also flows in inverter 159, from power-supply node 153 to ground terminal 154. Inverter 159 outputs a medium voltage between 0V and 3.3V to node N23.
Thus, a problem lies in that, when an inactivation signal of level H is output from common circuit 130 to exclusive circuit 150, through current flows between power-supply node 153 and ground terminal 154 in exclusive circuit 150.
When exclusive circuit 140 is inactivated to produce the DDR-SDRAM, no through current will flow in exclusive circuit 140 even if common circuit 130 outputs an inactivation signal of level H or L to exclusive circuit 140. Assuming that exclusive circuit 140 also includes inverters 156 and 159, common circuit 130 outputs a signal of level H having a voltage value of 2.5V, i.e., the external power-supply voltage, to exclusive circuit 140 as an inactivation signal. Power-supply node 153 is supplied with a voltage of 2.5V, so that P-channel MOS transistor 151 in inverter 156 will completely be turned off, while N-channel MOS transistor 152 is turned on. No through current flows in inverter 156, since P-channel MOS transistor 151 of the two MOS transistors constituting inverter 156 is completely turned off. Inverter 156 then outputs a voltage of 0V to node N22, turning on, P-channel MOS transistor 157 and turning off N-channel MOS transistor 158 in inverter 159. This prevents the through current from flowing in inverter 159.
Even when common circuit 130 outputs an inactivation signal of level L having a voltage of 0V, no through current will flow in exclusive circuit 140, since either one of P-channel MOS transistors 151, 157 or N-channel MOS transistors 152, 158, which constitute inverters 156 and 159, are completely turned off.
Thus, a problem arises that, when an inactivation signal of level H is used for inactivation, the through current flows only in exclusive circuit 150 connected to external power-supply line 160 where the external power-supply voltage varies to be either 2.5V or 3.3V.
In exclusive circuit 150, it may be possible to generate an inactivation signal having a voltage of 3.3V which is boosted by a voltage converter 210 shown in FIG. 21 in order to prevent the through current, and to output the generated inactivation signal to exclusive circuit 150. Voltage converter 210 includes P-channel MOS transistors 191, 193 and N-channel MOS transistors 192, 194, and an inverter 195. Each of the source terminals of P-channel MOS transistors 191, 193 is connected to a power-supply node 196, while each of the drain terminals of N-channel MOS transistors 192, 194 is connected to a ground terminal 197. Power-supply node 196 is supplied with a voltage of 3.3V. Thus, N-channel MOS transistor 192 is turned on, while N-channel MOS transistor 194 is turned off, by the voltage of 2.5V input from a node N24. A node N25 then comes to have a ground voltage and P-channel MOS transistor 193 is turned on. The voltage of 3.3V is output to a node N26.
When the signal of level H having the voltage of 3.3V generated in node N26 is input to exclusive circuit 150, P-channel MOS transistor 151 of inverter 156 and N-channel MOS transistor 158 of inverter 159 in exclusive circuit 150 are completely turned off, so that no through current flows in exclusive circuit 150.
However, a chip area would disadvantageously be increased if a plurality of voltage converters 210 shown in FIG. 21 are provided in a plurality of portions in the SDRAM.
It is, therefore, an object of the present invention to provide a semiconductor memory device in which no through current flows in an inactivated circuit, without increasing a chip area.
A semiconductor memory device according to the present invention functions as a first semiconductor memory device operating at a first external power-supply voltage or as a second semiconductor memory device operating at a second external power-supply voltage lower than the first external power-supply voltage. The first semiconductor memory device includes an external power-supply line supplied with the first external power-supply voltage, a voltage down converter connected to the external power-supply line and down-converts the first external power-supply voltage to an internal power-supply voltage, an internal power-supply line connected to the voltage down converter, a switch connected to the internal power-supply line, a first circuit connected to the switch and operated at the internal power-supply voltage, a second circuit connected to the internal power-supply line and operated at the internal power-supply voltage, and a third circuit connected to the external power-supply line and includes, at an input portion thereof, a circuit in which an N-channel MOS transistor or a P-channel MOS transistor is arranged between the external power-supply line and a ground terminal. The first circuit outputs a first functional signal to the second circuit and applies a first inactivation signal fixed to a ground voltage or a second inactivation signal fixed to the first external power-supply voltage to a gate terminal of the N-channel MOS transistor or the P-channel MOS transistor. The second semiconductor memory device includes an external power-supply line supplied with the second external power-supply voltage, a switch connected to the external power-supply line, a first circuit connected to the switch and operated at the second external power-supply voltage, a second circuit connected to the switch, and a third circuit connected to the external power-supply line and operated at the second external power-supply voltage. The first circuit outputs a second functional signal to the third circuit.
The semiconductor memory device according to the present invention is produced to have three types of circuits, that is, the first circuit operated at the internal power-supply voltage which has been down-converted from the first external power-supply voltage and at the second external power-supply voltage, the second circuit operated only at the internal power-supply voltage which has been down-converted from the first external power-supply voltage, and the third circuit operated only at the second external power-supply voltage. The first semiconductor memory device is produced using the first and second circuits. The first and second circuits are operated at the internal power-supply voltage which has been down-converted from the first external power-supply voltage, while the third circuit is supplied with the first external power-supply voltage. The third circuit includes, at the input portion thereof, a circuit in which an N-channel MOS transistor or a P-channel MOS transistor is arranged between the external power-supply line and the ground terminal. The first circuit outputs the first functional signal to the second circuit and applies the first inactivation signal fixed to the ground voltage or the second inactivation signal fixed to the first external power-supply voltage to a gate terminal of the N-channel MOS transistor or the P-channel MOS transistor in the third circuit. The second circuit is then activated, reading and writing data. The third circuit is inactivated, so that the P-channel MOS transistor or the N-channel MOS transistor is surely turned off.
The second semiconductor memory device is produced using the first and third circuits. The first and third circuits are operated at the second external power-supply voltage, and the second circuit is supplied with the second external power-supply voltage. The first circuit outputs the second functional signal to the third circuit. The third circuit is then activated, writing and reading data. Thus, according to the present invention, a circuit unnecessary for the semiconductor memory device can be inactivated, preventing through current from flowing in the inactivated circuit.
Preferably, the third circuit in the first semiconductor memory device includes, at an input portion thereof, an N-channel MOS transistor and a P-channel MOS transistor connected with each other in series between the external power-supply line and the ground terminal. The first circuit in the first semiconductor memory device applies the first inactivation signal or the second inactivation signal to the gate terminals of the N-channel MOS transistor and the P-channel MOS transistor.
The N-channel MOS transistor and the P-channel MOS transistor included in the third circuit of the first semiconductor memory device receive, at the gate terminals thereof, the first inactivation signal fixed to the ground voltage or the second inactivation signal fixed to the first external power-supply voltage from the first circuit, and either one of the transistors is turned off. Thus, according to the present invention, the through current can be prevented from flowing in the third circuit of the first semiconductor memory device.
Preferably, the second circuit in the second semiconductor memory device includes, at an input portion thereof, an N-channel MOS transistor and a P-channel MOS transistor connected with each other in series between the external power-supply line and the ground terminal. The first circuit in the second semiconductor memory device applies the first inactivation signal or a third inactivation signal fixed to the second external power-supply voltage to the gate terminals of the N-channel MOS transistor and the P-channel MOS transistor.
The N-channel MOS transistor and the P-channel MOS transistor included in the second circuit in the second semiconductor memory device receive, at the gate terminals thereof, the first inactivation signal fixed to a ground potential or the third inactivation signal fixed to the second external power-supply voltage from the first circuit, and either one of the transistors is surely turned off. Thus, according to the present invention, through current can be prevented from flowing in the second circuit in the second semiconductor memory device.
Preferably, the first circuit in the first semiconductor memory device applies the first inactivation signal generated based on the internal power-supply voltage to the gate terminals.
When the first semiconductor memory device is produced, the first external power-supply voltage is supplied and the first circuit is operated at the internal power-supply voltage that has been down-converted by the voltage down converter. The first circuit then generates the first inactivation signal fixed to the ground voltage based on the internal power-supply voltage, i.e., an operational power-supply of the circuit, and applies the signal to the gates of the P-channel MOS transistor and the N-channel MOS transistor. Thus, according the present invention, the first inactivation signal can also be generated if the internal power-supply voltage only is supplied.
Preferably, the first circuit includes an inverter generating the first inactivation signal based on the internal power-supply voltage.
In the first circuit, the inverter generates the first inactivation signal fixed to the ground voltage based on the internal power-supply voltage and outputs the signal to the third circuit. Thus, according to the present invention, the first inactivation signal fixed to the ground voltage can readily be generated with a simple configuration.
Preferably, the third circuit in the first semiconductor memory device includes, at an input portion thereof, an inverter to which the first or second inactivation signal is input.
The third circuit includes the inverter at the input portion thereof, and the inverter receives the first or second inactivation signal from the first circuit. The inverter is provided between an external power-supply line and a ground terminal, the external power-supply line being supplied with the first external power-supply voltage. As the inverter receives the first inactivation signal from the first circuit, the N-channel MOS transistor included in the inverter is turned off. Further, when the inverter receives the second inactivation signal from the first circuit, the P-channel MOS transistor also included in the inverter is turned off. Thus, according to the present invention, a circuit to be inactivated can be inactivated merely by providing the inverter at the input portion thereof, and through current therein can be prevented.
Preferably, the third circuit in the first semiconductor memory device includes a pulse generating circuit, including a plurality of inverters connected with each other in series, to which the first or the second inactivation signal is input, and also including an NOR gate to which the first or second inactivation signal and output signals of the plurality of inverters are input.
The third circuit includes a pulse generating circuit including a plurality of inverters and an NOR gate. The first or second inactivation signal is input to the plurality of inverters and the NOR gate, and the through current can be prevented from flowing in the plurality of inverters and in the NOR gate.
Preferably, the plurality of inverters constituting the pulse generating circuit include odd number of inverters, the odd number of inverters and the NOR gate receiving the first inactivation signal.
When the pulse generating circuit is constituted of the odd number of inverters and the NOR gate, the odd number of inverters and the NOR gate receive the first inactivation signal. The inverters and the NOR gate output a signal fixed to level H or L to inactivate the third circuit, and N-channel MOS transistors included in the inverters and the NOR gate are turned off. Thus, according to the present invention, through current can be prevented from flowing in the third circuit, as the pulse generating circuit generating a pulse is provided at the input portion thereof.
Preferably, the first circuit in the first semiconductor memory device includes an inactivation circuit outputting the first inactivation signal, and a common signal circuit outputting a common signal to the second and third circuits. The third circuit includes, at an input portion thereof, an NAND gate or an NOR gate.
The first circuit outputs the common signal to the second circuit, and outputs the common signal and the first inactivation signal to the third circuit. The second circuit is operated by the common signal that has been input. The third circuit includes the NAND gate or the NOR gate at the input portion thereof. An N-channel MOS transistor included in the NAND gate or the NOR gate is turned off by the first inactivation signal, independent of the level (H or L) of the common signal. Thus, according to the present invention, even when the second and third circuits receive the common signal, the third circuit unnecessary for production of the first semiconductor memory device can be inactivated, and through current can be prevented from flowing in the third circuit.
Preferably, when the first semiconductor memory device is produced, the inactivation circuit constituting the first circuit includes an inverter generating the first inactivation signal based on the internal power-supply voltage, and a third switch connected to the inverter.
When the first semiconductor memory device is produced, the third switch in the inactivation circuit is connected to the inverter. The inverter then outputs the first inactivation signal generated based on the internal power-supply voltage to the third circuit via the third switch. Further, the common signal circuit outputs the common signal to the second and third circuits. Thus, according to the present invention, the third circuit to which the common signal is input can be inactivated by the simple configuration, such as the one formed by merely generating the first inactivation signal by the inverter, and the through current in the third circuit can be prevented.
Preferably, a plurality of the second and third circuits are provided in the first semiconductor memory device, and the common signal circuit outputs two common signals to each of the plurality of second and third circuits.
In the first semiconductor memory device, a plurality of the second circuit to be activated and a plurality of the third circuit to be, inactivated are provided, and two common signals are input to the plurality of the second and third circuits. The first inactivation signal is input to the plurality of the third circuits. That is, the plurality of third circuits are inactivated by the first inactivation signal when the plurality of second circuits receive the two common signal and are operated. Thus, according to the present invention, in the semiconductor memory device in which the second circuit is operated by the two common signals, the third circuit is also inactivated, and the through current can be prevented.
Preferably, the common signal circuit outputs a read data signal. The first circuit outputs the read data signal to the second circuit, in which an input/output circuit outputs the read data signal to an input/output terminal. Thus, according to the present invention, the third circuit can be inactivated while data is actually being read, and the through current in the third circuit can be prevented.
Preferably, the switch is provided by an interconnection mask in a step of master slicing.
When the first or second semiconductor memory device is produced, the switch is connected to either one of the interconnections by the interconnection formed by the metal mask in the manufacturing process of the device. Thus, according to the present invention, it is possible to selectively produce one of two types of semiconductor memory devices in the manufacturing process.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.